Projects (From Ph.D. life):

Resolve: Hardware Sorter: Resolve provides a flexible hardware sorter library(targeted for FPGAs) and framework that generates customized hardware sorter. This is similar to std::sort routine found in standard template library (STL), which selects a specific sorting algorithm from a pool of sorting algorithms. For example, STL uses insertion sort for small lists (less than 15 elements), and then switches to merge sort for larger lists.

Composable High-level synthesis Templates: In this project, we explore theoretical framework of composing high-level synthesis templates to ease the development process of FPGA design with high-level synthesis. Our initial results demonstrate that composable high-level synthesis will work for application domains such as sorting and computer vision. As a future work, we plan to explore the high level synthesis template composition for deep learning and convolutional neural network.

Somewhat list of older projects:

See my old UCSD page